In conventional emitter coupled logic (ECL) circuits involving 2 or more logic levels the first level comprises a pair of differential, emitter coupled bipolar transistors having the circuit output taken as a differential voltage from the collectors which are tied to the positive supply through resistive loads. Complementary logic inputs are supplied to respective bases of the transistors. The common emitters are tied to the collector output of a similar transistor in the second level logic section. A common, substantially constant current source supplies current to the circuit. The base of the second level transistor is connected to the second level logic input. The transistors of the first level logic section may be selected or deselected by switching the second level transistor on or off by means of a high or low logic input to the second level logic input.
Transistors connected in cascade such as this require a supply voltage which is sufficiently high to accommodate the sum of the saturation voltages of the transistors in both logic levels. In devices fabricated from materials having a high saturation voltage such as AlGaAs/GaAs Heterojunction Bipolar Transistor (HBT) technology (typically 0.8 V CEsat and 1.5 V BEon) the power supply must be capable of supplying in the order of 6.5 V. This higher voltage naturally leads to potentially higher power consumption. Similarly performance of the logic functions may be adversely affected by device parameter variations such as current gain (Beta) when the transistors are connected in a cascade configuration. Additionally, the propagation delay of a cascade connected circuit is the sum of the delays through the transistors in each level due to the device transit time and parasitics.